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| 1 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 typical a pplica t ion fea t ures a pplica t ions descrip t ion 14-bit, 125msps/105msps/ 80msps low power octal adcs ltm9011-14, 125msps, 2-tone fft , f in = 70mhz and 75mhz the lt m ? 9011-14/ltm9010-14/LTM9009-14 are 8-chan- nel , simultaneous sampling 14-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. ac performance includes 73.1 db snr and 88 db spurious free dynamic range ( sfdr). low power consumption per channel reduces heat in high channel count applications. integrated bypass capacitance and flow-through pinout reduces overall board space requirements. dc specs include 1 lsb inl (typ), 0.3 lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . the digital outputs are serial lvds to minimize the num- ber of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl , or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 8-channel simultaneous sampling adc n 73.1db snr n 88db sfdr n low power: 140mw/113mw/94mw per channel n single 1.8v supply n serial lvds outputs: 1 or 2 bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for configuration n internal bypass capacitance, no external components n 140-pin (11.25mm 9mm) bga package n communications n cellular base stations n software defined radios n portable medical imaging n multichannel data acquisition n nondestructive t esting l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 9009101114 ta01b data serializer encode input serialized lvds outputs 1.8v v dd 1.8v ov dd out1a out1b out2a out2b out8a out8b data clock out frame gnd gnd 9009101114 ta01 s/h channel 1 analog input 14-bit adc core s/h channel 2 analog input 14-bit adc core s/h channel 8 analog input 14-bit adc core pll ? ? ? ? ? ? ? ? ? ? ? ?
ltm 9011-14/ ltm 9010-14/ ltm 9009-14 2 9009101114fa a bsolu t e maxi m u m r a t ings (notes 1, 2) p in c on f igura t ion o r d er i n f or m a t ion lead free finish tray part marking* package description temperature range ltm9011cy-14#pbf ltm9011cy-14#pbf ltm9011y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9011iy-14#pbf ltm9011iy-14#pbf ltm9011y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c ltm9010cy-14#pbf ltm9010cy-14#pbf ltm9010y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9010iy-14#pbf ltm9010iy-14#pbf ltm9010y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c ltm9009cy-14#pbf ltm9009cy-14#pbf ltm9009y14 140-lead (11.25mm 9mm 2.72mm) bga 0c to 70c ltm9009iy-14#pbf ltm9009iy-14#pbf ltm9009y14 140-lead (11.25mm 9mm 2.72mm) bga C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ supply voltages v dd , ov dd ................................................ C0. 3 v to 2v analog input voltage (a in + , a in C , par / ser , sense ) ( note 3) .......... C 0.3 v to (v dd + 0.2 v) digital input voltage ( enc + , enc C , cs , sdi , sck ) ( note 4) .................................... C 0.3 v to 3.9 v sdo ( note 4) ............................................. C 0.3 v to 3.9 v digital output voltage ................ C0.3 v to ( ov dd + 0.3 v) operating temperature range ltm 9 011 c, ltm 9010 c, ltm 9009 c ......... 0 c to 70 c ltm 9 011 i, ltm 9010 i, ltm 9009 i ......... C 40 c to 85 c storage temperature range .................. C 55 c to 125 c 1 p c d e f g h j k l m n a b 1098765432 bga package 140-lead (11.25mm 9.00mm 2.72mm) top view t jmax = 150c, ja = 30c/w, jc = 25c/w, jb = 15c/w, jcbottom = 12c/w 3 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltm9011-14 ltm9010-14 LTM9009-14 units min typ max min typ max min typ max resolution ( no missing codes) l 14 14 14 bits integral linearity error differential analog input (note 6) l C4.1 1.2 4.1 C3.25 1 3.25 C2.75 1 2.75 lsb differential linearity error differential analog input l C0.9 0.3 0.9 C0.8 0.3 0.8 C0.8 0.3 0.8 lsb offset error (note 7) l C12 3 12 C12 3 12 C12 3 12 mv gain error internal reference external reference l C2.6 C1.3 C1.3 0 C2.6 C1.3 C1.3 0 C2.6 C1.3 C1.3 0 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 35 25 35 25 35 25 ppm/c ppm/c gain matching external reference 0.2 0.2 0.2 %fs offset matching 3 3 3 mv transition noise external reference 1.2 1.2 1.2 lsb rms a nalog i npu t the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode ( a in + + a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps 155 130 100 a a a i in1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i in2 par /ser input leakage current 0 < par /ser < v dd l C3 3 a i in3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz ltm 9011-14/ ltm 9010-14/ ltm 9009-14 4 9009101114fa dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltm9011-14 ltm9010-14 LTM9009-14 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 70.8 73.1 73 72.6 70.6 73 72.9 72.6 69.7 73 72.9 72.5 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 70mhz input 140mhz input l 69 88 85 82 71 88 85 82 74 88 85 82 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5mhz input 70mhz input 140mhz input l 81 90 90 90 81 90 90 90 82 90 90 90 dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 68.4 73 72.6 72 69.7 73 72.6 72 69.6 72.9 72.6 72 dbfs dbfs dbfs crosstalk, near channel 10mhz input (note 12) C90 C90 C90 dbc crosstalk, far channel 10mhz input (note 12) C105 C105 C105 dbc i n t ernal r e f erence c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v 5 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 digi t al i npu t s a n d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance 3.5 pf digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance 3 pf digital d ata outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 6 9009101114fa p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltm9011-14 ltm9010-14 LTM9009-14 units min typ max min typ max min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 582 632 476 508 395 450 ma i ovdd digital supply current 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 54 98 62 108 52 96 62 106 50 94 58 104 ma ma p diss power dissipation 2-lane mode, 1.75ma mode 2-lane mode, 3.5ma mode l l 1145 1224 1249 1332 950 1030 1026 1105 801 880 914 997 mw mw p sleep sleep mode power 2 2 2 mw p nap nap mode power 170 170 170 mw p diffclk power decrease with single- ended encode mode enabled (no decrease for sleep mode) 40 40 40 mw ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltm9011-14 ltm9010-14 LTM9009-14 units min typ max min typ max min typ max f s sampling frequency (notes 10,11) l 5 125 5 105 5 80 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2 4 4 100 100 4.52 2 4.76 4.76 100 100 5.93 2 6.25 6.25 100 100 ns ns t ap sample-and-hold acquisition delay time 0 0 0 ns symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2-lanes, 16-bit serialization 2-lanes, 14-bit serialization 2-lanes, 12-bit serialization 1-lane, 16-bit serialization 1-lane, 14-bit serialization 1-lane, 12-bit serialization 1/(8 ? f s ) 1/(7 ? f s ) 1/(6 ? f s ) 1/(16 ? f s ) 1/(14 ? f s ) 1/(12 ? f s ) s s s s s s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles 7 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 symbol parameter conditions min typ max units spi port timing (note 8) t sck sck period write mode read back mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid read back mode, c sdo = 20pf, r pullup = 2k l 125 ns ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltm9011), 105mhz (ltm9010), or 80mhz (ltm9009), 2-lane output mode, differential enc + / enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v, f sample = 125mhz (ltm9011), 105mhz (ltm9010), or 80mhz (ltm9009), 2-lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifications are totals for the entire device, not per channel. note 10: recommended operating conditions. note 11: the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns. note 12: near-channel crosstalk refers to ch. 1 to ch.2, and ch.7 to ch.8. far- channel crosstalk refers to ch.1 to ch.7, ch.1 to ch.8, ch.2 to ch.7, and ch.2 to ch.8. ltm 9011-14/ ltm 9010-14/ ltm 9009-14 8 9009101114fa 2-lane output mode, 14-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 sample n-3 n+1 n+2 n 9009101114 td02 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 out#a ? out#a + fr ? fr + d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 out#b ? out#b + note that in this mode fr + /fr ? has two times the period of enc + /enc ? ti m ing diagra m s 2-lane output mode, 16-bit serialization* analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 *see the digital outputs section sample n-5 sample n-4 n+1 n 9009101114 td01 d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 out#a ? out#a + fr ? fr + d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 out#b ? out#b + 9 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 t i m ing d iagra m s 2-lane output mode, 12-bit serialization 1-lane output mode, 16-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 9009101114 td03 d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 out#a ? out#a + fr + fr ? d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 out#b ? out#b + analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9009101114 td04 d1 d0 0 0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled ltm 9011-14/ ltm 9010-14/ ltm 9009-14 10 9009101114fa t i m ing d iagra m s 1-lane output mode, 14-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9009101114 td06 d3 d2 d1 d0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 1-lane output mode, 12-bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 9009101114 td07 d5 d4 d3 d2 d13 d12 d11 d10 d12 d11 d9 d8 d7 d6 d5 d4 d3 d2 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 11 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 9009101114 td08 cs sck sdi r/w sdo high impedance t i m ing d iagra m s ltm 9011-14/ ltm 9010-14/ ltm 9009-14 12 9009101114fa typical p er f or m ance c harac t eris t ics ltm9011-14: integral nonlinearity (inl) ltm9011-14: differential nonlinearity (dnl) ltm9011-14: 8k point fft , f in = 5mhz, C1dbfs, 125msps output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 9009101114 g01 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 9009101114 g02 frequency (mhz) ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 9009101114 g03 0 10 20 30 40 50 60 ltm9011-14: 8k point fft , f in = 30mhz, C1dbfs, 125msps ltm9011-14: 8k point fft , f in = 70mhz, C1dbfs, 125msps ltm9011-14: 8k point fft , f in = 140mhz, C1dbfs, 125msps ltm9011-14: 8k point 2-tone fft , f in = 70mhz, 75mhz, C7dbfs per tone, 125msps ltm9011-14: shorted input histogram frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 9009101114 g04 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 9009101114 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 9009101114 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 9009101114 g07 output code 8178 1000 0 3000 2000 count 4000 5000 6000 8180 8182 8184 8186 9009101114 g08 13 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 typical p er f or m ance c harac t eris t ics input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 9009101114 g09 ltm9011-14: snr vs input frequency, C1dbfs, 2v range, 125msps ltm9011-14: sfdr vs input level, f in = 70mhz, 2v range, 125msps ltm9011-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 9009101114 g11 dbfs dbc input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 9009101114 g10 ltm9011-14: sfdr vs input frequency, C1dbfs, 2v range, 125msps i ovdd vs sample rate, 5mhz sine wave input, C1dbfs ltm9011-14: snr vs sense, f in = 5mhz, C1dbfs sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 9009101114 g15 sample rate (msps) 580 560 540 520 500 480 460 440 420 i vdd (ma) 0 25 50 75 100 125 9009101114 g13 sample rate (msps) 100 80 60 40 20 0 i ovdd (ma) 0 25 50 75 100 125 9009101114 g14 1-lane, 1.75ma 2-lane, 3.5ma 2-lane, 1.75ma 1-lane, 3.5ma input level (dbfs) 60 50 40 30 20 10 0 80 70 snr (dbc and dbfs) ?60 ?50 ?40 ?30 ?20 ?10 0 9009101114 g12 dbfs dbc ltm9011-14: snr vs input level, f in = 70mhz, 2v range, 125msps ltm 9011-14/ ltm 9010-14/ ltm 9009-14 14 9009101114fa typical p er f or m ance c harac t eris t ics ltm9010-14: integral nonlinearity (inl) ltm9010-14: differential nonlinearity (dnl) ltm9010-14: 8k point fft , f in = 5mhz, C1dbfs, 105msps output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 9009101114 g16 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 9009101114 g17 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 9009101114 g18 ltm9010-14: shorted input histogram output code 8195 1000 0 3000 2000 count 4000 5000 6000 8197 8199 8201 8203 9009101114 g23 ltm9010-14: 8k point fft , f in = 70mhz, C1dbfs, 105msps ltm9010-14: 8k point fft , f in = 140mhz, C1dbfs, 105msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 9009101114 g20 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 9009101114 g21 ltm9010-14: 8k point 2-tone fft , f in = 70mhz, 75mhz, C7dbfs per tone, 105msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 9009101114 g22 ltm9010-14: 8k point fft , f in = 30mhz, C1dbfs, 105msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 9009101114 g19 15 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 ltm9010-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs ltm9010-14: sfdr vs input level, f in = 70mhz, 2v range, 105msps typical p er f or m ance c harac t eris t ics input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 9009101114 g26 dbfs dbc input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 9009101114 g24 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 9009101114 g25 ltm9010-14: snr vs input frequency, C1dbfs, 2v range, 105msps ltm9010-14: sfdr vs input frequency, C1dbfs, 2v range, 105msps sample rate (msps) 460 440 420 400 380 360 340 320 i vdd (ma) 0 25 50 75 100 9009101114 g27 ltm9010-14: snr vs sense, f in = 5mhz, C1dbfs sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 9009101114 g28 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 16 9009101114fa typical p er f or m ance c harac t eris t ics LTM9009-14: 8k point 2-tone fft , f in = 70mhz, 75mhz, C7dbfs per tone, 80msps LTM9009-14: shorted input histogram LTM9009-14: 8k point fft , f in = 30mhz, C1dbfs, 80msps LTM9009-14: 8k point fft , f in = 70mhz, C1dbfs, 80msps LTM9009-14: 8k point fft , f in = 140mhz, C1dbfs, 80msps LTM9009-14: integral nonlinearity (inl) LTM9009-14: differential nonlinearity (dnl) LTM9009-14: 8k point fft , f in = 5mhz, C1dbfs, 80msps output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 9009101114 g30 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 9009101114 g31 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 9009101114 g32 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 9009101114 g33 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 9009101114 g34 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 9009101114 g35 output code 8184 1000 0 3000 2000 count 4000 5000 6000 8186 8188 8190 8192 9009101114 g36 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 9009101114 g29 17 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 typical p er f or m ance c harac t eris t ics LTM9009-14: i vdd vs sample rate, 5mhz sine wave input, C1dbfs dco cycle-cycle jitter vs serial data rate LTM9009-14: snr vs sense, f in = 5mhz, C1dbfs sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 9009101114 g41 LTM9009-14: sfdr vs input level, f in = 70mhz, 2v range, 80msps input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 9009101114 g39 dbfs dbc input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 9009101114 g38 LTM9009-14: sfdr vs input frequency, C1dbfs, 2v range, 80msps input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 9009101114 g37 LTM9009-14: snr vs input frequency, C1dbfs, 2v range, 80msps serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 9009101114 g42 sample rate (msps) 380 360 340 320 300 280 i vdd (ma) 0 20 40 60 80 9009101114 g40 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 18 9009101114fa p in func t ions a in1 + (b2): channel 1 positive differential analog input. a in1 C ( b 1): channel 1 negative differential analog input. v cm12 (b3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 1 and 2. v cm is internally bypassed to ground with a 0.1 f ceramic capacitor. no external capacitance is required. a in2 + (c2): channel 2 positive differential analog input. a in2 C ( c 1): channel 2 negative differential analog input. a in3 + (e2): channel 3 positive differential analog input. a in3 C ( e 1): channel 3 negative differential analog input. v cm34 (f3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 3 and 4. v cm is internally bypassed to ground with a 0.1 f ceramic capacitor. no external capacitance is required. a in4 + (g2): channel 4 positive differential analog input. a in4 C ( g 1): channel 4 negative differential analog input. a in5 + (h1): channel 5 positive differential analog input. a in5 C ( h 2): channel 5 negative differential analog input. v cm56 (j3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 5 and 6. v cm is internally bypassed to ground with a 0.1 f ceramic capacitor. no external capacitance is required. a in6 + (k1): channel 6 positive differential analog input. a in6 C ( k 2): channel 6 negative differential analog input. a in7 + ( m 1): channel 7 positive differential analog input. a in7 C ( m 2): channel 7 negative differential analog input. v cm78 (n3): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 7 and 8. v cm is internally bypassed to ground with a 0.1 f ceramic capacitor. no external capacitance is required. a in8 + (n1): channel 8 positive differential analog input. a in8 C ( n 2): channel 8 negative differential analog input v dd ( d3, d4, e3, e4, k3, k4, l3, l4): 1.8 v analog power supply. v dd is internally bypassed to ground with 0.1f ceramic capacitors. enc + (p5): encode input. conversion starts on the rising edge. enc C (p6): encode complement input. conversion starts on the falling edge. csa (l5): in serial programming mode, ( par /ser = 0v), cs a is the serial interface chip select input for registers controlling channels 1, 4, 5 and 8. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in parallel programming mode ( par / ser = v dd ), cs selects 2- lane or 1- lane output mode. cs can be driven with 1.8v to 3.3v logic. csb (m5): in serial programming mode, ( par /ser = 0v), cs b is the serial interface chip select input for registers controlling channels 2, 3, 6 and 7. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in parallel programming mode ( par / ser = v dd ), cs selects 2- lane or 1- lane output mode. cs can be driven with 1.8v to 3.3v logic. sck (l6): in serial programming mode, ( par /ser = 0v), sck is the serial interface clock input. in parallel programming mode ( par /ser = v dd ), sck selects 3.5ma or 1.75 ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi (m6): in serial programming mode , ( par /ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in parallel programming mode ( par /ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd ( see pin configuration table): adc power ground. use multiple vias close to pins. 19 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 p in func t ions ov dd ( g9, g10): output driver supply. ov dd is internally bypassed to ground with a 0.1f ceramic capacitor. sdoa ( e6): in serial programming mode , ( par / ser = 0 v), sdoa is the optional serial interface data output for registers controlling channels 1, 4, 5 and 8. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain n-channel mosfet output that requires an external 2k pull-up resistor from 1.8 v to 3.3 v. if read back from the mode control registers is not needed, the pull-up resis- tor is not necessary and sdo can be left unconnected. in parallel programming mode ( par /ser = v dd ), sdoa is an input that enables internal 100 termination resistors on the digital outputs of channels 1, 4, 5 and 8. when used as an input, sdo can be driven with 1.8 v to 3.3 v logic through a 1k series resistor. sdob (d6): serial data output pin for channels 2, 3, 6 and 7. see description for sdoa. par / ser ( a 7): programming mode selection pin. connect to ground to enable the serial programming mode. csa, cs b, sck, sdi, sdoa and sdob become a serial interface that control the a/d operating modes. connect to v dd to enable parallel programming mode where csa, cs b, sck, sdi, sdoa and sdob become parallel logic inputs that control a reduced set of the a/d operating modes. par / ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref (b6): reference voltage output. v ref is internally bypassed to ground with a 1 f ceramic capacitor, nomi- nally 1.25v. sense (c5): reference programming pin. connecting sense to v dd selects the internal reference and a 1 v input range. connecting sense to ground selects the internal reference and a 0.5 v input range. an external reference between 0.625 v and 1.3 v applied to sense selects an input range of 0.8 ? v sense . sense is internally bypassed to ground with a 0.1f ceramic capacitor. lvds outputs all pins in this section are differential lvds outputs. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. out 1a C / out 1a + , out 1b C / out 1b + ( e 7/e 8, c 8/d 8): serial data outputs for channel 1. in 1- lane output mode only out1a C /out1a + are used. out 2a C / out 2a + , out 2b C / out 2b + ( b 8/a 8, d 7/c 7): serial data outputs for channel 2. in 1- lane output mode only out2a C /out2a + are used. out3a C /out3a + , out3b C /out3b + ( d10/d9, e10/e9): serial data outputs for channel 3. in 1- lane output mode only out3a C /out3a + are used. out 4a C / out 4a + , out 4b C / out 4b + ( c 9/c 10, f 7/f 8): serial data outputs for channel 4. in 1- lane output mode only out4a C /out4a + are used. out 5a C / out 5a + , out 5b C / out 5b + ( j 8/j 7, k 8/k 7): serial data outputs for channel 5. in 1- lane output mode only out5a C /out5a + are used. out 6a C / out 6a + , out 6b C / out 6b + ( k 9/k 10, l 9/l 10): serial data outputs for channel 6. in 1- lane output mode only out6a C /out6a + are used. out 7a C / out 7a + , out 7b C / out 7b + ( m 7/l 7, p 8/n 8): serial data outputs for channel 7. in 1- lane output mode only out7a C /out7a + are used. out8a C /out8a + , out8b C /out8b + ( l8/m8, m10/m9): serial data outputs for channel 8. in 1- lane output mode only out8a C /out8a + are used. fra C /fra + (h7/h8): frame start outputs for channels 1, 4, 5 and 8. frb C /frb + (j9/j10): frame start outputs for channels 2, 3, 6 and 7. dcoa C /dcoa + (g8/g7): data clock outputs for channels 1, 4, 5 and 8. dcob C /dcob + ( f10, f9): data clock outputs for chan- nels 2, 3, 6 and 7. ltm 9011-14/ ltm 9010-14/ ltm 9009-14 20 9009101114fa 1 2 3 4 5 6 7 8 9 10 a gnd gnd gnd gnd gnd gnd par /ser o2a + gnd gnd b a in1 C a in1 + v cm12 gnd gnd v ref gnd o2a C gnd gnd c a in2 C a in2 + gnd gnd sense gnd o2b + o1b C o4a C o4a + d gnd gnd v dd v dd gnd sdob o2b C o1b + o3a + o3a C e a in3 C a in3 + v dd v dd gnd sdoa o1a C o1a + o3b + o3b C f gnd gnd v cm34 gnd gnd gnd o4b C o4b + dcob + dcob C g a in4 C a in4 + gnd gnd gnd gnd dcoa + dcoa C ov dd ov dd h a in5 + a in5 C gnd gnd gnd gnd fra C fra + gnd gnd j gnd gnd v cm56 gnd gnd gnd o5a + o5a C frb C frb + k a in6 + a in6 C v dd v dd gnd gnd o5b + o5b C o6a C o6a + l gnd gnd v dd v dd cs a sck o7a + o8a C o6b C o6b + m a in7 + a in7 C gnd gnd cs b sdi o7a C o8a + o8b + o8b C n a in8 + a in8 C v cm78 gnd gnd gnd gnd o7b + gnd gnd p gnd gnd gnd gnd clk + clk C gnd o7b C gnd gnd top view of bga package (looking through component). p in c on f igura t ion table 21 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 func t ional b lock diagra m figure 1. functional block diagram diff ref amp ref buffer refh refl range select 1.25v reference gnd v dd /2 9009101114 f01 sense v ref mode control registers ov dd = 1.8v v dd = 1.8v out1a + out1a ? out1b + out1b ? s/h ch 1 analog input 14-bit adc core out2a + out2a ? out2b + out2b ? s/h ch 2 analog input 14-bit adc core out3a + out3a ? out3b + out3b ? s/h ch 3 analog input 14-bit adc core out4a + out4a ? out4b + out4b ? s/h ch 4 analog input 14-bit adc core out5a + out5a ? out5b + out5b ? s/h ch 5 analog input 14-bit adc core out6a + out6a ? out6b + out6b ? s/h ch 6 analog input 14-bit adc core out7a + out7a ? out7b + out7b ? s/h ch 7 analog input 14-bit adc core out8a + out8a ? out8b + out8b ? s/h ch 8 analog input 14-bit adc core dcoa dcob fra frb enc + enc ? sdoa sdob sdi sck csa csb par/ ser vcm12 vcm34 vcm56 vcm78 pll data serializer ltm 9011-14/ ltm 9010-14/ ltm 9009-14 22 9009101114fa a pplica t ions i n f or m a t ion converter operation the ltm9011-14/ltm9010-14/LTM9009-14 are low power, 8-channel, 14-bit, 125msps/105msps/80msps a/d converters that are powered by a single 1.8 v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter perfor- mance, or single- ended for lower power consumption. the digital outputs are serial lvds to minimize the number of data lines. each channel outputs two bits at a time (2-lane mode). at lower sampling rates there is a one bit per channel option (1-lane mode). many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits ( figure 2). the inputs should be driven differentially around a common mode voltage set by the appropriate v cm output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5 v. there should be 180 phase difference between the inputs. the eight channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc low pass filter right at the analog inputs. this lowpass filter isolates the drive cir cuitry from the a/d sample- and- hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its opti- mal dc level. at higher input frequencies a transmission line balun transformer ( figures 4 to 6) has better balance, resulting in lower a/d distortion. figure 2. equivalent input circuit. only one of the eight analog channels is shown c sample 3.5pf r on 25 r on 25 v dd v dd ltm9011-14 a in + 9009101114 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltm9011-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 9009101114 f03 23 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a pplica t ions i n f or m a t ion amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. see back page for a dc-coupled example. figure 4. recommended front end circuit for input frequencies from 70mhz to 170mhz 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 9009101114 f04 ltm9011-14 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 9009101114 f05 ltm9011-14 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 9009101114 f06 ltm9011-14 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm ltm9011-14 9009101114 f07 ? ? + + analog input high speed differential amplifier 0.1f at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driving the a/d. figure 5. recommended front end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front end circuit for input frequencies above 300mhz figure 7. front end circuit using a high speed differential amplifier ltm 9011-14/ ltm 9010-14/ ltm 9009-14 24 9009101114fa v ref 1.25v refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v refl 0.1f 2.2f internal adc high reference buffer 9009101114 f08 ltm9011-14 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f 0.1f a pplica t ions i n f or m a t ion figure 8. reference circuit figure 9. using an external 1.25v reference reference the ltm9011-14/ltm9010-14/LTM9009-14 has an inter - nal 1.25 v voltage reference. for a 2 v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2 v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). sense 1.25v external reference 1f 9009101114 f09 ltm9011-14 the input range can be adjusted by applying a voltage to sense that is between 0.625 v and 1.30 v. the input range will then be t v sense . the reference is shared by all eight adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref , sense, refh and refl pins are internally bypassed, as shown in figure 8. 25 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a pplica t ions i n f or m a t ion encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu- soidal, pecl, or lvds encode inputs (figures 12 and 13). figure 13. pecl or lvds encode drive figure 12. sinusoidal encode drive 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ltm9011-14 9009101114 f12 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 9009101114 f13 ltm9011-14 v dd ltm9011-14 9009101114 f10 enc ? enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc ? 9009101114 f11 0v 1.8v to 3.3v ltm9011-14 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode the encode inputs are internally biased to 1.2 v through 10k equivalent resistance. the encode inputs can be taken above v dd ( up to 3.6 v), and the common mode range is from 1.1 v to 1.6 v. in the differential encode mode, enc C should stay at least 200 mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single- ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode ltm 9011-14/ ltm 9010-14/ ltm 9009-14 26 9009101114fa a pplica t ions i n f or m a t ion input. enc + can be taken above v dd ( up to 3.6 v) so 1.8 v to 3.3 v cmos logic levels can be used. the enc + threshold is 0.9 v. for good jitter performance enc + should have fast rise and fall times. clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop ( pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. digital outputs the digital outputs of the ltm9011-14/ltm9010-14/ LTM9009-14 are serialized lvds signals. each channel outputs two bits at a time (2- lane mode). at lower sam- pling rates there is a one bit per channel option (1-lane mode). the data can be serialized with 16, 14, or 12-bit serialization ( see the timing diagrams section for details). note that with 12- bit serialization the two lsbs are not availablethis mode is included for compatibility with 12-bit versions of these parts. the output data should be latched on the rising and falling edges of the data clock out ( dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2-lane, 14- bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps, so the maximum sample rate of the adc will de- pend on the serialization mode as well as the speed grade of the adc ( see table 1). the minimum sample rate for all serialization modes is 5msps. by default the outputs are standard lvds levels : 3.5ma output current and a 1.25 v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. table 1. maximum sampling frequency for all serialization modes. note that these limits are for the ltm9011-14. the sampling frequency for the slower speed grades cannot exceed 105mhz ( ltm9010-14) or 80mhz ( LTM9009-14). serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial d ata rate 2-lane 16-bit serialization 125 4 ? f s f s 8 ? f s 2-lane 14-bit serialization 125 3.5 ? f s 0.5 ? f s 7 ? f s 2-lane 12-bit serialization 125 3 ? f s f s 6 ? f s 1-lane 16-bit serialization 62.5 8 ? f s f s 16 ? f s 1-lane 14-bit serialization 71.4 7 ? f s f s 14 ? f s 1-lane 12-bit serialization 83.3 6 ? f s f s 12 ? f s 27 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a pplica t ions i n f or m a t ion programmable lvds output current the default output driver current is 3.5 ma. this current can be adjusted by control register a2 in the serial pro- gramming mode. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4 ma and 4.5 ma. in the parallel programming mode, the sck pin can select either 3.5ma or 1.75ma. optional lvds driver internal termination in most cases, using just an external 100? termina- tion resistor will give excellent lvds signal integrity. in addition, an optional internal 100? termination resistor can be enabled by serially programming mode con- trol register a2. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma, 2.1 ma or 2.5ma lvds output current modes. d ata format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2 s complement format can be selected by serially programming mode control register a1. digital output randomizer inter ference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive- or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. the output randomizer is enabled by serially programming mode control register a1. table 2. output codes vs input voltage a in + C a in C (2v range) d13-d0 (offset binary) d13-d0 (2s complement) >1.000000v +0.999878v +0.999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 +0.000122v +0.000000v C0.000122v C0.000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C0.999878v C1.000000v 29 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a pplica t ions i n f or m a t ion table 4. serial programming mode register map ( par /ser = gnd) register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. the adc is momentarily placed in sleep mode. after the reset spi write command is complete, bit d7 is automatically set back to zero. the reset register is write only. bits 6-0 unused, dont care bits. register a1 (cs a): format and power-down register (address 01h with csa = gnd) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_8 nap_5 nap_4 nap_1 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format bits 4-0 sleep: nap_x sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 4 in nap mode 0x1xx = channel 5 in nap mode 01xxx = channel 8 in nap mode 1xxxx = sleep mode. channels 1, 4, 5 and 8 are disabled note: any combination of channels can be placed in nap mode. are ignored. the data transfer ends when cs is taken high again. the first bit of the 16- bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data ( d7:d0) will be writ- ten to the register set by the address bits ( a6:a0). if the r/w bit is high, data in the register set by the address bits ( a6:a0) will be read back on the sdo pin ( see the timing diagrams section). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open- drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2 k pull- up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull- up resistor is needed. table 4 shows a map of the mode control registers. ltm 9011-14/ ltm 9010-14/ ltm 9009-14 30 9009101114fa a pplica t ions i n f or m a t ion register a1 (cs b): format and power-down register (address 01h with csb = gnd) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_7 nap_6 nap_3 nap_2 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. bit 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 5 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format bits 4-0 sleep: nap_4:nap_1 sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 2 in nap mode 0xx1x = channel 3 in nap mode 0x1xx = channel 6 in nap mode 01xxx = channel 7 in nap mode 1xxxx = sleep mode. channels 2, 3, 6 and 7 are disabled note: any combination of channels can be placed in nap mode. register a2: output mode register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 ilvds2 ilvds1 ilvds0 termon outoff outmode2 outmode1 outmode0 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bits 7-5 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0 ma l vds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x the current set by ilvds2:ilvds0. internal termination should only be used with 1.75ma, 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. bits 2-0 outmode2:outmode0 digital output mode control bits 000 = 2-lanes, 16-bit serialization 001 = 2-lanes, 14-bit serialization 010 = 2-lanes, 12-bit serialization 011 = not used 100 = not used 101 = 1-lane, 14-bit serialization 110 = 1-lane, 12-bit serialization 111 = 1-lane, 16-bit serialization 31 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 a pplica t ions i n f or m a t ion register a3: test pattern msb register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on bit 6 unused, dont care bit. bit 5-0 tp13:tp8 test pattern data bits (msb) tp13:tp8 set the test pattern for data bit 13 (msb) through data bit 8. register a4: test pattern lsb register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 note that csa controls channels 1, 4, 5 and 8, csb controls channels 2, 3, 6 and 7. bit 7-0 tp7:tp0 test pattern data bits (lsb) tp7:tp0 set the test pattern for data bit 7 through data bit 0 (lsb). software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. grounding and bypassing the ltm9011-14/ltm9010-14/LTM9009-14 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. bypass capacitors are integrated inside the package; ad- ditional capacitance is optional. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. the pin assignments of the ltm9011-14/ltm9010-14/ LTM9009-14 allow a flow- through layout that makes it possible to use multiple parts in a small area when a large number of adc channels are required. the ltm9011 module has similar layout rules to other bga pack- ages. the layout can be implemented with 6 mil blind vias and 5 mil traces. the pinout has been designed to minimize the space required to route the analog and digital traces. the analog and digital traces can essen- tially be routed within the width of the package. this allows multiple packages to be located close together for high channel count applications. trace lengths for the analog inputs and digital outputs should be matched as well as possible. ltm 9011-14/ ltm 9010-14/ ltm 9009-14 32 9009101114fa a pplica t ions i n f or m a t ion heat transfer most of the heat generated by the ltm9011-14/ltm9010-14/ LTM9009-14 is transferred from the die through the bot- tom of the package onto the printed circuit board. the ground pins should be connected to the internal ground planes by multiple vias. table 5. internal trace lengths pin name length (mm) pin name length (mm) pin name length (mm) pin name length (mm) e7 01a C 1.775 k8 05b C 0.379 e1 a in3 C 2.491 f10 dcob C 1.811 e8 01a + 1.947 k7 05b + 0.528 e2 a in3 + 2.505 f9 dcob + 1.812 c8 01b C 1.847 k9 06a C 1.866 g1 a in4 C 3.376 h7 fra C 1.117 d8 01b + 1.850 k10 06a + 1.865 g2 a in4 + 3.372 h8 fra + 1.038 b8 02a C 3.233 l9 06b C 2.268 h2 a in5 C 3.301 j9 frb C 1.644 a8 02a + 3.246 l10 06b + 2.267 h1 a in5 + 3.346 j10 frb + 1.643 d7 02b C 0.179 m7 07a C 1.089 k2 a in6 C 2.506 a7 par /ser 3.838 c7 02b + 1.127 l7 07a + 0.179 k1 a in6 + 2.533 l6 sck 0.240 d10 03a C 2.126 p8 07b C 3.281 m2 a in7 C 3.198 e6 sdoa 0.453 d9 03a + 2.177 n8 07b + 3.149 m1 a in7 + 3.214 d6 sdob 0.274 e10 03b C 1.811 l8 08a C 1.862 n2 a in8 C 4.726 m6 sdi 1.069 e9 03b + 1.812 m8 08a + 1.847 n1 a in8 + 4.691 b3 v cm12 3.914 c9 04a C 3.199 m10 08b C 4.021 p6 clk C 4.106 f3 v cm34 0.123 c10 04a + 3.196 m9 08b + 4.016 p5 clk + 4.106 j3 v cm56 0.079 f7 04b C 0.706 b1 a in1 C 4.689 l5 cs a 0.919 n3 v cm78 3.915 f8 04b + 0.639 b2 a in1 + 4.709 m5 cs b 1.162 j8 05a C 0.392 c1 a in2 C 4.724 g8 dcoa C 1.157 j7 05a + 0.436 c2 a in2 + 4.769 g7 dcoa + 1.088 table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. these should be added to the pcb trace lengths for best matching. the material used for the substrate is bt (bismaleimide- triazine), supplied by mitsubishi gas and chemical. in the dc to 125 mhz range, the speed for the analog input signals is 198 ps/in or 7.795 ps/mm. the speed for the digital outputs is 188.5ps/in or 7.417ps/mm. 33 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 top side typical a pplica t ions silkscreen top ltm 9011-14/ ltm 9010-14/ ltm 9009-14 34 9009101114fa t ypical a pplica t ions inner layer 2 inner layer 3 35 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 inner layer 5 t ypical a pplica t ions inner layer 4 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 36 9009101114fa t ypical a pplica t ions bottom side silkscreen bottom 37 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 t ypical a pplica t ion ltm9011-14 schematic e3 v + 3v to 6v clk + clk + gnd term sdob 3.3 aux jp6 1 2 3 r8 1k r11 10k en dis term sdoa 3.3 aux jp3 1 2 3 1 2 3 1 2 3 r3 1k en dis r5 31.6k 1% r13 31.6k 1% r4 10k lane csb jp3 1 2 3 r1 1k 1 lane 2 lane +1.8v +1.8v +1.8v +1.8v ilvds sck jp5 r7 1k 1.7ma 3.5ma lane csa jp2 r2 1k 1 lane 2 lane +1.8v par/ser par/ser par/ser sense vref sci sck csa csb sdoa sdob mosi jp4 r6 1k par ser r9 100 e1 ext ref r10 1k c1 2.2f, 0603 a1 a2 a3 a4 a5 a6 b4 b5 b7 c3 c4 c6 d1 d2 d5 e5 f1 f2 f4 f5 f6 g3 g4 g5 g6 h3 h4 h5 h6 j1 j2 j4 j5 j6 k5 k6 l1 l2 m3 m4 n4 n5 n6 n7 p1 p2 p3 p4 p7 a9 a10 b9 b10 h9 h10 n9 n10 p9 p10 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a7 c5 b6 m6 l6 l5 m5 e6 d6 ltm9011-14 +1.8v r20 100 r14 (opt) l1 (opt) 1 2 3 5 4 r18 (opt) r25 (opt) c2 (opt) r24 (opt) c13 100f 10v r28 3k 9009101114 ta02 out1a + out1a ? out1b + out1b ? out1a + out1a ? out1b + out1b ? e8 e7 d8 c8 out2a + out2a ? out2b + out2b ? out2a + out2a ? out2b + out2b ? a8 b8 c7 d7 out3a + out3a ? out3b + out3b ? out3a + out3a ? out3b + out3b ? d9 d10 e9 e10 out4a + out4a ? out4b + out4b ? out4a + out4a ? out4b + out4b ? c10 c9 f8 f7 out5a + out5a ? out5b + out5b ? out5a + out5a ? out5b + out5b ? j7 j8 k7 k8 out6a + out6a ? out6b + out6b ? out6a + out6a ? out6b + out6b ? k10 k9 l10 l9 ain1 + ain1 ? vcm12 ain1 + ain1 ? vcm12 b2 b1 b3 ain2 + ain2 ? ain2 + ain2 ? c2 c1 ain3 + ain3 ? vcm34 ain3 + ain3 ? vcm34 e2 e1 f3 vcm12 ain4 + ain4 ? ain4 + ain4 ? g2 g1 ain5 + ain5 ? vcm56 ain5 + ain5 ? vcm56 h2 h1 j3 ain6 + ain6 ? ain6 + ain6 ? k1 k2 ain8 + ain8 ? vcm78 ain8 + ain8 ? vcm78 n1 n2 n3 ain7 + ain7 ? ain7 + ain7 ? m1 m2 clk + clk ? clk + clk ? p5 p6 out7a + out7a ? out7b + out7b ? out7a + out7a ? out7b + out7b ? m8 l8 m9 m10 fra + fra ? frb + frb ? fra + fra ? frb + frb ? h8 h7 j10 j9 dcoa + dcoa ? dcob + dcob ? dcoa + dcoa ? dcob + dcob ? g7 g8 f9 f10 +1.8vo +1.8vo +1.8vo g9 g10 +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v +1.8v d3 d4 e3 e4 k3 k4 l3 l4 c7 4.7pf c5 4.7pf r23 5.1 r37 100 r17 5.1 r22 49.9 1% r21 49.9 1% c9 0.01f r27 (opt) c6 0.01f (opt) c3 0.01f r26 (opt) r16 (opt) r15 (opt) j2 j1 e4 t1 maba- 007159-000000 fb1 blm31pg330sn1l fb2 blm31pg330sn1l c4 0.01f c8 0.01f r19 100 +1.8v +1.8vo lt3080edd c11 1f 0603 1 2 3 9 out out out out c56 0.1f c14 0.1f c10 4.7f 6.3v 0603 c12 1f 0603 4 set 6 nc 7 8 5 in in vctrl r29 180k 1% + +1.8v +1.8v c18 (opt) c23 (opt) c15 (opt) c19 (opt) c17 (opt) (same for other channels) r30 0 0603 r36 0 0603 r31 0 0805 r37 0 0805 r32 0 0603 r38 0 0603 in + in ? r48 100 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 38 9009101114fa p ackage descrip t ion notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 5. primary datum -z- is seating plane 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view x aaa z 3 see notes bga 140 0709 rev a tray pin 1 bevel package in tray loading orientation component pin ?a1? ?b (140 places) d detail b package side view m x yzddd m zeee 0.4 ? 140x symbol a a1 a2 b b1 d e e d1 e1 aaa bbb ccc ddd eee min 2.57 0.35 2.22 0.45 0.35 nom 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 max 2.87 0.45 2.42 0.55 0.45 0.15 0.10 0.12 0.15 0.08 notes dimensions total number of balls: 140 y aaa z e e a2 d1 b e e1 ltmxxxxxx module detail a suggested pcb layout top view 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 5.200 4.400 4.400 5.200 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 4 pin ?a1? corner 1 p detail a c d e f g h j k l m n a b 10 9 8 7 6 5 4 3 2 pin 1 package bottom view b a z detail b substrate 0.27 ? 0.37 1.95 ? 2.05 // bbb z a1 b1 ccc z mold cap bga package 140-lead (11.25mm 9.00mm 2.72mm) (reference ltc dwg # 05-08-1849 rev a) please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 39 9009101114fa ltm 9011-14/ ltm 9010-14/ ltm 9009-14 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 9/11 updated functional block diagram 21 ltm 9011-14/ ltm 9010-14/ ltm 9009-14 40 9009101114fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0911 rev a ? printed in usa r ela t e d p ar t s part number description comments adcs ltc2170-14/ltc2171- 14/ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2170-12/ltc2171- 12/ltc2172-12 12-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw/234mw/360mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-12/ltc2174- 12/ltc2175-12 12-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw/481mw/567mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-14/ltc2174- 14/ltc2175-14 14-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw/481mw/567mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/hz total input noise, 40ma supply current per amplifier, 3 mm 4mm qfn-20 ltc6605-7/ ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 signal chain receivers ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers t ypical a pplica t ion single-ended to differential conversion using ltc6409 and 50mhz lowpass filter (only one channel shown). filter for use at 92.16msps ltm9010-14 f3 f1 f2 c1 c2 b3 b1 b2 v cm12 a in2 + a in2 ? a in3 + a in3 ? v cm34 a in4 + a in4 ? a in8 + a in8 ? a in1 + a in1 ? o1a + o1a ? dco + dco ? fr + fr ? g2 g1 n1 n2 h7 h8 g8 g7 e7 e8 clk + clk ? p5 p6 b6 c5 1.8v 1.8v sense v dd v ref ov dd 33pf 100pf 150pf 180nh 180nh 3.3v 180nh 180nh 150pf 150 474 37.4 37.4 out ? out + v ocm in + v + in ? 474 75 75 66.9 66.9 0.1f 0.8pf 0.8pf 68pf 68pf 0.1f 9009101114 ta03 ? ? ? ? + 150 shdn gnd 49.9 50 ? ? ? ltc6409 |
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